Add workaround for errata 764081 of Cortex-A75
authorLouis Mayencourt <[email protected]>
Wed, 20 Feb 2019 12:11:41 +0000 (12:11 +0000)
committerLouis Mayencourt <[email protected]>
Tue, 26 Feb 2019 15:53:57 +0000 (15:53 +0000)
commit5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8
treef2144f3d54b1dfd7625bdcf08438573f569d2101
parente6cab15dc710e2270d869c3fa76ed8d0d4943b66
Add workaround for errata 764081 of Cortex-A75

Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.

Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <[email protected]>
docs/cpu-specific-build-macros.rst
include/arch/aarch64/arch.h
lib/cpus/aarch64/cortex_a75.S
lib/cpus/cpu-ops.mk
lib/el3_runtime/aarch64/context_mgmt.c